The present invention relates to a semiconductor integrated circuit and particularly to a clock synchronization type semiconductor memory including an input circuit having low current dissipation. Low power consumption is desirable for a synchronous dynamic random access memory (hereinafter referred to as SDRAM). Therefore, power consumption for an input buffer of a SDRAM must be lowered.
FIG. 1 illustrates a conventional input buffer circuit. The input buffer circuit comprises an input circuit 1 and a latch circuit 2. The input circuit 1 receives an input signal (for example, address signal, control signal, data signal) to be applied to an external terminal. And the latch circuit 2 latches an output signal from the input circuit 1 in synchronization with an internal clock signal iclk. An output of the latch circuit 2 is supplied to an internal circuit. In FIG. 1, numeral 3 designates a clock buffer circuit which receives the external clock CLK applied to the clock signal terminal and supplies the internal clock iclk to internal circuits.
The input circuit 1 comprises, for example, a CMOS inverter. Moreover, the latch circuit 2 comprises inverters 4, 5 and a transfer switch. The inverter 4 is connected to the output of the input circuit 1. The inverter 5 has an input and an output which are cross-connected to the output and the input of the inverter 4. The transfer switch which is provided between the output of the inverter 5 and input of the inverter 4 and is composed of a PMOS transistor P01 and a NMOS transistor n01 connected in parallel. This transfer switch turns ON/OFF in response to the internal clock iclk.
The input circuit 1 receives the input signal applied to the external terminal and outputs a signal which has an inverted logic level to the input signal. When the transfer switch is turned ON in response to the internal clock iclk synchronized with the leading edge of an external clock signal CLK, the latch circuit 2 latches an output of the input circuit 1.
In the input buffer circuit of the related art as illustrated in FIG. 1, the input circuit 1 is always connected to the power supply line. Therefore, the input circuit 1 of the related art consumes a large amount of current. As an example other than FIG. 1, an input circuit has been known in which current consumption is reduced by making non-active the input circuit during a power-down mode.
However, lately, a desire for low current consumption in a SDRAM is moreover increasing and a certain measure for low current consumption is also required for the input buffer circuit.
Therefore, it is an object of the present invention to provide a semiconductor integrated circuit which assures low current consumption and reduces current consumption in the clock synchronization type semiconductor integrated circuit. Moreover, the present invention is intended to provide an input circuit for an SDRAM that assures low current consumption and reduces current consumption.
The inventors of the present invention have investigated the following to achieve the desired feature explained above.
FIG. 2 is a timing diagram for explaining the setup time and hold time in the input circuit. In the clock synchronization type semiconductor integrated circuit, the input signal (address signal, control signal, etc.) is fetched and latched in response to rise timing of the external clock CLK. The input signal is required to maintain its logic value during the setup time and hold time as explained below.
Namely, in the example of FIG. 1, in order for the latch circuit 2 to latch the input signal applied to the external terminal in synchronization with the external clock CLK, the following is required. That is, the input signal applied to the external terminal must reach the input of the latch circuit 2 via the input circuit 1 and define the logic value of the input signal at the input of the latch circuit 2 before the latch circuit 2 starts a latch operation in response to the rise of the internal clock iclk.
Here, the input signal applied to the external terminal is sent to the latch circuit 2 via several circuits such as the input circuit 1 or the like. Moreover, in FIG. 1, a certain period is necessary until the input of latch circuit 2 is defined from start of signal output from the input circuit 1. Therefore, as illustrated in FIG. 2, the logic value of the input signal to be applied to the external terminal must be defined at least before the setup time ts rather than the rise of the external clock CLK.
Meanwhile, the input signal of the latch circuit 2 must be held until the latch output of the latch circuit 2 is defined. Namely, in FIG. 1, a certain time is required until the clock buffer 3 generates the internal clock iclk from the external clock CLK and the predetermined time is also required until the internal clock iclk is transferred to the latch circuit 2 from the clock buffer 3. If the input signal at the latch circuit 2 ceases immediately after the rise of external clock CLK, the input signal at the input node of the latch circuit is already lost when the latch circuit 2 starts the latch operation in response to the internal clock iclk. Thus, the latch circuit 2 cannot properly latch the input signal.
Therefore, the input signal applied to the external terminal must be held for the period corresponding to the hold time shown in FIG. 2, even after the external clock CLK rises.
For the reasons explained above, the setup time ts and hold time tH are defined to the input circuit with reference to the rise timing of the external clock signal. And during this period ts+tH, the logic level of the input signal at the external signal terminal must be maintained.
Therefore, the input circuit illustrated in FIG. 1 must be activated during the period corresponding to the setup time and hold time. However, if the input circuit 1 is activated during any other period, not including ts+tH, the input circuit 1 needlessly consumes current.
The present invention saves current consumption of the input circuit 1 by monitoring the input circuit 1 and ensuring that it is activated only during the required period that includes setup time and hold time, which is shorter than one period of the external clock. According to the present invention, the input circuit 1 is activated only for the required period and is inactive during any other period.
Namely, in view of solving the problem explained above, the input circuit in the present invention is intermittently activated during the period corresponding to the setup time and hold time of the input circuit. Since the input circuit is activated for the period corresponding to the setup time and hold time, the input signal can be correctly latched in synchronization with the clock signal as in the case of the related art. Meanwhile, since the input circuit is in an inactive condition during any other period, current consumption in the input circuit is reduced.
Additionally, an output of the input circuit of the present invention is in a high impedance condition when the circuit is in the inactive condition. Therefore, when the input circuit is in the inactive condition, a current is prevented from flowing across the power supply line and output line of the input circuit, thereby reducing current consumption.
Moreover, the present invention also comprises a latch circuit for latching an output signal from the input circuit. The second inverter of which output is connected to the input of a latch circuit among two inverters forming the latch circuit is in a high impedance condition when the latch circuit is inactive. Therefore, when the latch circuit is inactive, a current is prevented from flowing via the second inverter across the input wiring of the latch circuit and power supply line. Thereby, current consumption is reduced.
Moreover, the present invention also comprises an activation signal generating circuit for generating the activation signal to activate the input circuit. This activation signal generating circuit comprises a delay circuit for adjusting the activation timing of the activation signal. Delay time of this delay circuit may be programmed and such delay time is programmed to transition the activation signal to the active condition before the setup time of the input circuit. Thus, current consumption of the input circuit can be reduced by setting the delay time of delay circuit.
Moreover, the other embodiment is structured in such a manner that the delay time of the delay circuit is changed in response to a CAS latency. The maximum frequency of the external clock is changed in response to the selected CAS latency. An effect of the low current consumption of the input circuit can further be improved by changing over the delay time of delay circuit (namely, activation timing of the activation signal) in response to the maximum frequency of the external clock.
Moreover, the activation signal generating circuit of the other embodiment executes the control so that the period of active condition of the activation signal becomes constant independent of the frequency of the input external clock. The maximum effect of the above-mentioned current consumption reduction effect of the input circuit can be extracted by considering the period of active condition to correspond to the total time of the setup time and hold time of the input circuit.